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Freescale Semiconductor /MKE15Z7 /TSI /SINC

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Interpret as SINC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SSC_CONTROL_OUT 0 (0)SINC_VALID 0 (0)SINC_OVERFLOW_FLAG 0 (0)SWITCH_ENABLE 0 (00000)DECIMATION0 (0)ORDER 0 (0000)CUTOFF

CUTOFF=0000, ORDER=0, DECIMATION=00000, SWITCH_ENABLE=0, SINC_OVERFLOW_FLAG=0, SSC_CONTROL_OUT=0, SINC_VALID=0

Description

TSI SINC filter Register

Fields

SSC_CONTROL_OUT

SSC_CONTROL_OUT

0 (0): SSC output value is 0.

1 (1): SSC output value is 1.
SINC_VALID

SINC_VALID

0 (0): SINC filter is disabled.

1 (1): SINC filter is enabled.
SINC_OVERFLOW_FLAG

SINC_OVERFLOW_FLAG

0 (0): The counter result has no overflow occurence in the last scan process.

1 (1): The counter result has an overflow occurence in the last scan process.
SWITCH_ENABLE

SWITCH_ENABLE

0 (0): SSC function is disabled.

1 (1): SSC function is enabled.
DECIMATION

DECIMATION

0 (00000): The TSI_DATA[TSICNT] bits is the counter value of 1 scan period.

1 (00001): The TSI_DATA[TSICNT] bits is the counter value of 2 scan periods.

2 (00010): The TSI_DATA[TSICNT] bits is the counter value of 3 scan periods.

3 (00011): The TSI_DATA[TSICNT] bits is the counter value of 4 scan periods.

4 (00100): The TSI_DATA[TSICNT] bits is the counter value of 5 scan periods.

5 (00101): The TSI_DATA[TSICNT] bits is the counter value of 6 scan periods.

6 (00110): The TSI_DATA[TSICNT] bits is the counter value of 7 scan periods.

7 (00111): The TSI_DATA[TSICNT] bits is the counter value of 8 scan periods.

8 (01000): The TSI_DATA[TSICNT] bits is the counter value of 9 scan periods.

9 (01001): The TSI_DATA[TSICNT] bits is the counter value of 10 scan periods.

10 (01010): The TSI_DATA[TSICNT] bits is the counter value of 11 scan periods.

11 (01011): The TSI_DATA[TSICNT] bits is the counter value of 12 scan periods.

12 (01100): The TSI_DATA[TSICNT] bits is the counter value of 13 scan periods.

13 (01101): The TSI_DATA[TSICNT] bits is the counter value of 14 scan periods.

14 (01110): The TSI_DATA[TSICNT] bits is the counter value of 15 scan periods.

15 (01111): The TSI_DATA[TSICNT] bits is the counter value of 16 scan periods.

16 (10000): The TSI_DATA[TSICNT] bits is the counter value of 17 scan periods.

17 (10001): The TSI_DATA[TSICNT] bits is the counter value of 18 scan periods.

18 (10010): The TSI_DATA[TSICNT] bits is the counter value of 19 scan periods.

19 (10011): The TSI_DATA[TSICNT] bits is the counter value of 20 scan periods.

20 (10100): The TSI_DATA[TSICNT] bits is the counter value of 21 scan periods.

21 (10101): The TSI_DATA[TSICNT] bits is the counter value of 22 scan periods.

22 (10110): The TSI_DATA[TSICNT] bits is the counter value of 23 scan periods.

23 (10111): The TSI_DATA[TSICNT] bits is the counter value of 24 scan periods.

24 (11000): The TSI_DATA[TSICNT] bits is the counter value of 25 scan periods.

25 (11001): The TSI_DATA[TSICNT] bits is the counter value of 26 scan periods.

26 (11010): The TSI_DATA[TSICNT] bits is the counter value of 27 scan periods.

27 (11011): The TSI_DATA[TSICNT] bits is the counter value of 28 scan periods.

28 (11100): The TSI_DATA[TSICNT] bits is the counter value of 29 scan periods.

29 (11101): The TSI_DATA[TSICNT] bits is the counter value of 30 scan periods.

30 (11110): The TSI_DATA[TSICNT] bits is the counter value of 31 scan periods.

31 (11111): The TSI_DATA[TSICNT] bits is the counter value of 32 scan periods.
ORDER

ORDER

0 (0): Using 1 order sinc filter.

1 (1): Using 2 order sinc filter.
CUTOFF

CUTOFF

0 (0000): div=1.

1 (0001): div=2.

2 (0010): div=4.

3 (0011): div=8.

4 (0100): div=16.

5 (0101): div=32.

6 (0110): div=64.

7 (0111): div=128.

8 (1000): NC.

9 (1001): NC.

10 (1010): NC.

11 (1011): NC.

12 (1100): NC.

13 (1101): NC

14 (1110): NC.

15 (1111): NC.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data